1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to an input buffer for a semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices commonly include input buffers for converting the voltage level of a signal input from an external circuit to a voltage level suitable for an internal circuit. The input buffer operates to correctly detect the voltage level of the external signal to allow the semiconductor memory device to operate within normal parameters.
FIG. 1 is a circuit diagram of an N-type input buffer 101 of a conventional semiconductor memory device. Referring to FIG. 1, a conventional N-type semiconductor memory device 101 includes an NMOS transistor 111 for receiving external data IN, an NMOS transistor 112 for receiving a reference voltage Vref, a current mirror 131 constituted of PMOS transistors 121 and 122, a PMOS transistor 123 for providing a supply voltage Vdd to the current mirror 131 in response to an external control signal PBPUB, and an inverter 141 for inverting data from a node N1 and for outputting output data OUT of the N-type input buffer 101.
In the case where the external input data IN is logic high in the N-type input buffer 101, assuming that there is noise present in a ground voltage Vss, it takes longer for the data output from the node N1 to transition from logic high to logic low due to the noise. Therefore, the length of time, or "skew", for the data output from the node N1 to transition from logic high to logic low, i.e. "high-voltage skew", becomes larger. Accordingly, the set-up time and hold time margins of the data OUT output of the N-type input buffer 101 are reduced.
FIG. 2 is a circuit diagram of a P-type input buffer of a conventional semiconductor memory device. Referring to FIG. 2, a conventional P-type input buffer 201 includes a PMOS transistor 211 for receiving external data, a PMOS transistor 212 for receiving a reference voltage, a current mirror 231 constituted of NMOS transistors 221 and 222, a PMOS transistor 213 for providing a supply voltage Vdd to the PMOS transistors 211 and 212 in response to the external control signal PBPUB, and an inverter 241 for inverting data from a node N2 and for outputting the output data OUT of the P-type input buffer 201.
In the case where the external data IN is logic low in the P-type input buffer 201, assuming the presence of noise in the supply voltage Vdd, it takes longer for the data output from the node N2 to transition from logic low to logic high due to the noise. Therefore, the skew time for the data output from the node N2 to transition from logic low to logic high, i.e. "low-voltage skew", becomes larger. Accordingly, the set-up time and hold time margins of the data OUT output of the P-type input buffer 201 are reduced.
As mentioned above, according to the conventional technology, since the high-voltage skew or low-voltage skew of the data OUT output from the input buffers 101 and 201 is relatively larger, the set-up time and hold time margins of the data OUT are reduced. Furthermore, it is increasingly difficult to reduce the skew of the data OUT as the trend toward ever-lower supply voltages Vdd continues.